With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, the integration of resistors into prior art semiconductor structures becomes increasingly problematic. Resistors are most often integrated into a semiconductor structure during middle of the line (MOL) process flow. The MOL process flow generally includes those set of process steps used in the creation of the gate (CA) contacts and the source/drain (CB) contacts of transistors.
Prior art semiconductor structures require a dielectric layer disposed between the gate structure of the transistors and the resistors in order to prevent the resistors from electrically shorting to the gate. Problematically however, this increases the thickness of the dielectric layers in the MOL architecture, which exacerbates dimensional changes in width between the top and bottom of the CA and CB contacts. This is due to the fact that etching is never completely in a vertical direction. That is, any etching process (even an anisotropic RIE etch process) will always have some horizontal etch component to it. Accordingly, the top of a CA or a CB contact will always be larger than the bottom. The thicker the dielectric layers that must be etched through in order to form the CA and CB contacts, the greater the dimensional changes that will occur. These dimensional changes can have a negative effect on quality and reliability.
Also problematically in prior art semiconductor devices, the transistors and other like devices over which a resistor is disposed are rendered non-functional or disabled. This is because the resistor prevents any electrical connections from reaching the components disposed underneath them. So a Fin Field Effect Transistor (FinFET), for example, which can be made operational with CA contacts to its gate and CB contacts to its source/drain regions, is rendered non-functional if it is covered by a resistor that blocks such contacts from being made. Moreover, resistors generally have an increasingly large foot print and tend to cover larger number of devices with scaling due to the fact that their resistivity is fixed.
Accordingly, there is a need for a semiconductor structure that does not require a dielectric layer between resistors and gates in order to prevent electrical shorting. Additionally there is a need for a semiconductor structure wherein the resistors do not disable the components disposed below them.